As for the show, Moscow International Motor Show 2013(MIMS) is regarded highly in the automotive industry in Russia. Last year, the exhibitors consisted of 1,379 companies from 35 countries and 15,717 guests from 52 countries participated in this event. 99.6% of visitors were industry professionals. With its specific geographic location, MIMS is truly a trans-lateral gateway for automotive businesses. If you are looking for Acrosser’s products or other innovative automotive components from Taiwan, do not miss the Taiwan Pavilion (Pavilion 8 Hall 3, booth number: R111) this year!
AR-V6100FL features fanless operation with Intel Core i7-2710QE 45W CPU. Its excellent thermal design makes it a popular industry choice for In-Vehicle PCs. The efficiency of heat dissipation also contributes to its high performance under rugged automotive environments. Another fascinating feature of AR-V6100FL is its smart power management function. Acrosser built a comprehensive power management subsystem solution, allowing users to select the best setting for the power management mode to meet specific application demands.
Most engineers and system integrators find it troublesome when installing car computers in their business vehicle. How often did hardware configuration or software programming take away from their business? Above all these worries, establishing steady power management becomes the most important issue before integrating the entire system. Acrosser’s In-Vehicle computer offers 6 stunning power management traits to overcome these difficulties.
Feature 1: Wide Range Power Input
Vehicles usually take 2 types of battery voltage: 12V or 24V. However, Acrosser’s power manage subsystem has a wide range for power inputs that cater to both batteries. This could also protect the system from unstable power surges during the vehicle’s operation.
Feature 2: Battery Monitoring
Large energy consumption may occur while operating the car computer. To prevent the power loss, Acrosser’s In-Vehicle computer offers low voltage protection to monitor the main battery. Once the voltage goes below its pre-set value, the computer will shut down and save the energy for vehicle use.
Please contact ACROSSER Technology for further consultations, volume quotes, or any other questions.
A portable atomic clock is just the ticket for many UAVs, and the more SWaP-optimized the better. The Chip-Scale Atomic Clock (CSAC) fits the bill with the low power draw and accurate performance inherent in its design.
Unmanned Aerial Vehicles (UAVs) began as tools for military surveillance. As their capabilities expanded, they found usage in civilian applications such as border patrols and drug interdiction, while on the military side the expanded capabilities led to missions using armed UAVs. refer to http://smallformfactors.com/articles/chip-scale-swap-design-challenges/#at_pco=cfd-1.0
ANR-IB75N1/A/B is a rackmount platform (440x372x44mm) which can be installed in the 19” rack. It can carry a 3rd generation Intel Core i i3, i5, i7, or Pentium processors to deliver higher efficiency, increased processing throughput, and improved performance on applications. ANR-IB75N1/A/B also comes equipped with a maximum 16GB DDR3 memory and optional 2 or 4 x SFP and 8 x LAN ports. System Integrators can select different configurations for their network appliances. It offers the best P/P ratio in applications like the UTM, IDS/IPS, VPN, Firewall, Anti-Virus, Anti-Spam, RSA gateway, QoS, streaming.
ANR-IB75N1/A/B uses 80 Plus PSU which reduces energy consumption and helps protect the environment. The software and hardware configurable LAN bypass feature also prevents communication breaks due to power loss or system hang-ups. In addition to Intel long life support chipsets, ANR-IB75N1/A/B is designed with a long-term support of 5 years.
Key features: 1. Support 3rd generation Intel Core i LGA1155 i3/i5/i7/Pentium cores processor 2. Intel B75 Chipset 3. DDRIII DIMM x 2, up to 16GB memory. 4. Intel 82576EB x 2 Fiber ports 5. Intel 82574L 10/100/1000Mbps x 8 ports 6. Two pairs LAN ports support bypass feature (LAN 1/2 + LAN 3/4) 7. LAN bypass can be controlled by BIOS and Jumper 8. CF socket, 2.5” HDD x 2, SATA III x 1, SATA II X1 9. Console, VGA (pinhead), USB 3.0 x 2 (2 x external) 10. Support boot from LAN, console redirection 11. Equipped with 80 Plus Bronze PSU to decrease CO2 dissipation and protect our environment 12. LCM module to provide user-friendly interface 13. Standard 1U rackmount size
A new All-in-OneGaming Board, the AMB-A55EG1. AMB-A55EG1 features AMD Embedded G-Series T56N 1.65GHz dual-core APU, two DDR3-1333 SO-DIMM, which provides great computing and graphic performance is suitable for casino gaming and amusement applications. It is designed to comply with the most gaming regulations including GLI, BMM, and Comma 6A. AMB-A55EG1 is specifically designed to be a cost competitive solution for the entry-level gaming market.
AMB-A55EG1 utilizes the functions of an X86 platform, 72-pin Gaming I/O interface, intrusion detection and also various security options, and a complete line of Application Programming Interfaces to create smoother gaming development.
Acrosser AMB-A55EG1 is powered by AMD low power G-Series T56N dual core platform that uses an AMD Radeon HD 6320 graphic controller. The DirectX® 11 support lets you enjoy awesome graphics performance, stunning 3D visual effects and dynamic interactivity. Discrete-level GPU with OpenGL 4.0 and OpenCL™ 1.1 support device provides the tools to build the designs of tomorrow, today.
In conclusion, AMB-A55EG1 bridges Acrosser’s innovated gaming solutions and AMD Embedded G-Series APU to bring the optimum combination of computing power, graphic performance, and gaming features. Acrosser supports all gaming products in Windows XP Pro, XP embedded and mainstream Linux operation system with complete software development kit (SDK). In addition, Acrosser’s gaming platforms have a minimum 5-year availability to fulfill the demand of long term supply in gaming industry.
For more information on AMB-A55EG1 or any other products, please contact your local Acrosser sales channel or logon to our website: www.acrosser.com
FPGAs have become some of the most importantdrivers for developmentof leading edge semiconductor technology. The complexity ofprogrammabledevices, and their integration of diverse high-performance functions, provides excellent vehicles
for testing new processes. It’s no accident that Intel has selected
Achronix and Tabula, both makers of programmable devices, as the only
partners that have been granted access to their 22 nm 3D Tri-Gate
(FinFET) process. In February, Intel also announced an agreement with
Altera, which will enable the company to manufacture FPGAs using their
next-generation 14 nm Tri-Gate process.
In parallel with driving manufacturing,FPGA
technology development must also include enhancements to design tools
and flows. As vendors strive to make their devices moreSoC- and ASIC-like, they are also adopting standards and collaborating withEDA
companies to integrate their tools more seamlessly. These
collaborations are producing great benefits for designers, as FPGA
design methodologies are leading the way in areas that the EDA industry
has long been promising new capabilities, such as in Electronic System
Level (ESL) synthesis, IP integration and re-use, and higher-level tools
for software/hardware co-design.
FPGA
design methodologies have long integrated EDA point tools, such as
simulation and PCB design, into FPGA vendor’s design platforms. Now,
vendors such asSynopsys,
with their Synplicity tools, and Xilinx with Vivado, are collaborating
to build more complete integrated top-to-bottom flows. To address the
greater complexity of FPGAs that may now contain up to two million
equivalent logic cells, Synopsys has added Hierarchical Project Management(HPM) to Synplicity. HPM supports distributed design teams and parallel development, enabling partitioning ofRTLand sharing of design debug tasks. Xilinx has adopted the industry-standardSynopsys Design Constraint(SDC) timing constraints (to replace Xilinx proprietary UDC) in a design flow that can be driven from standardVerilog HDL.
EASING IP INTEGRATION
Easier integration and re-use of semiconductor IP, especially when sourcing from multiple vendors, has been one of the greatest challenges to SoC designers andEDA toolflows. With the advent of higher capacity FPGA-based SoCs that utilize embedded ARM cores, those same challenges are now extended to the world of FPGA design.
One of the methods that the EDA and IP industry has developed to ease the problem is the adoption of a standard for IP description formats, the IP-XACT standard. IP-XACT was originally developed by the SPIRIT Consortium of companies that included ARM,Cadence, Mentor, and Synopsys. SPIRIT merged with EDA Standards organization Accellera in 2010. The IEEE adopted IP-XACT as the IEEE Std-1685 in 2009, and has made the specification available todownloadfree from the organization’s website. The specification defines the use of XML meta-data to document the characteristics of IP, and an API to enable integration with EDA tools.
Xilinx has announced that they are supporting IP-XACT in their new Vivado IP Integrator (IPI), to ease the integration of their own and third-party IP. IPI is available to Xilinx’s early access customers along with the release of the latest revision of the Vivado Design Suite 2013.1. In ademonstration videofrom Xilinx, IPI appears to provide a very easy to use schematic-driven graphical user interface, which enables “correct-by-construction” block-level assembly of complex designs. Xilinx says the system can also be run in a tcl script-driven mode.
IPI enables users to select IP blocks from a library, place the blocks on a schematic, and then simply point and click to draw the interconnections between blocks, I/Opins, and AXI busses. The system prevents invalid connections from being made, and alerts the user to errors with a built-in validation function. A user can start by selecting the target FPGA from the Vivado library or choose one of Xilinx’s evaluation boards, which will include information on other onboardcomponentssuch as external DRAM, so that interfaces can be included as part of the FPGA design process. Designer assistance is provided to ease construction of larger functional blocks, such as MicroBlaze processor subsystems. After completion of the block-level design, and final DRC validation, users can utilize Vivado’s HDL generation functions to create Verilog orVHDLto drive synthesis and place and route.
INDUSTRY STANDARDS ENABLE HIGHER LEVELS OF ABSTRACTION
Building on their 2011 acquisition of AutoESL, Xilinx also says that they have expanded their C/C++ system-level design library forHigh-Level Synthesis(HLS) in the new Vivado release. Xilinx is targeting the growing market for embedded vision applications, following on their participation as a founding member of theEmbedded Vision Alliance, with support for industry standard floating point math.h operations and real-time video processing functions. Designers of embedded vision systems will be able to utilize Vivado HLS integrated with the Open Source Computer Vision Library provided by the OpenCV organization. OpenCV is an open source BSD-licensed library of computer vision functions, which supports Windows,Linux, Mac,Androidand Apple iOS operating systems. Vivado users will be able to develop embedded vision applications for the dual-core ARM Cortex A9 processor system in Zynq FPGAs, augmented with special-purpose hardware accelerators built in the programmable logic fabric.
Today’s most advanced SoCs arehighly parallelheterogeneous computing systems, which challenge the traditional low-level HDL-based programmingmodel. Altera has been leading the FPGA industry in promoting the use ofOpenCL, an industry standard for parallel programming of systems containing a mix of CPUs, GPUs, and DSPs, which is maintained by the Khronos Group. In November last year, Altera released their first SDK for OpenCL to early access customers, as part of the version 12.1 update of their Quartus II suite of design tools. Hardware platforms that support the OpenCL SDK are becoming available, starting with the Nallatech 385 PCIe accelerator card, which employs Altera Stratix V FPGAs.
THE FUTURE OF FPGAS
Advances inFPGA toolsand flows are good news for designers of programmable logic systems as well as ASIC and SoC designers. At a recent Synopsys User Group tutorial on the Synplicity-Vivado flow, the large majority of attendees were involved in FPGA prototyping, where the latest high-capacity FPGAs have become critical tools fordesign validationand signoff for complex SoCs. By utilizing the same design languages and standards for both ASIC and FPGAdesign, much duplication of effort can be eliminated and faster time-to-market will result.
802.11 networks are becoming nearly ubiquitous in many enterprise settings and can often be tapped to solve embedded problems in the same location. In this example, a logistics cart used for warehouse operations becomes 802.11 enabled, improving the efficiency of a critical process.
In a tough economy with increased competition from global markets, companies are forced to do more with less. Supply chainmanagement is one area where companies realize this challenge. Organizations are continually struggling to ship more orders, decrease processing time, and increase order accuracy, all the while reducing costs. The nature of order processing has changed as well. With just-in-time and lean manufacturing techniques becoming common practices, distribution warehouses often need to process a high volume of small orders, which often involve a large mix of products, adding further complexity to the process.
The end result is that the order picking process is increasingly challenging. In a typical warehouse or distribution center, studies have shown that order picking can consume as much as two-thirds of the facility’s operating cost and time. As a result, companies are continually looking for new technologies and innovations to automate the order picking process.
Pick-to-light goes paperless …
In the first days of order picking, an order list was created, and a fast-footed person would chase down all of the parts, collect the correct quantities of each part, and transport them to the shipping area. This batch process saw many improvements, including techniques to optimize the ideal locations for each part and algorithms to minimize the travel distance of the person picking the order.
Computer and networking technologies facilitated the development of an innovative system known as pick-to-light that significantly improved this process. The pick-to-light system provides an automated, paperless, order picking solution. With this system, the order list is sequenced to LED displays that direct the order picker to a location and indicate the quantity of parts to pick. This system significantly increased order accuracy and reduced order picking times by providing the shortest pick path through the warehouse.
The next step was extending this system to leverage a mobilevehicleor cart for pickers to gather more parts in a highly effective manner. In the mid-1990s, Innovative Picking Technologies (IPTI) developed the first pick-to-light cart called the RF Batch PicKart (Figure 1), a patented paperless order fulfillment system that utilizes PICK-MAX pick-to-light displays mounted to a mobile cart.
Figure 1:The RF Batch PicKart was the first pick-to-light cart that enabled a paperless order fulfillment system.
The first versions of the RF PicKart used proprietary RFradiosto communicate. The radios were mostly 900 MHz point-to-point. Although these radios could provide awirelessdata link to the cart, they were expensive to deploy, and the data throughput was generally slow.
… then moves to 802.11
With the growing popularity of IEEE 802.11 wireless networking, IPTI found that customers usually had asecureand reliable 802.11 Wireless Local Area Network (WLAN) infrastructure that could be leveraged. IPTI migrated the design of the RF PicKart to 802.11b/g, providing customers with high-speed data transfers, seamless data connections to back-end server processing, and much lower price points.
IPTI performed extensive system testing to make sure that thewireless networkcould:
Allow robust communications to multiple mobile carts in a warehouse environment
Extend to provide complete coverage in large warehouse environments
Handle the normal shock/vibration issues with robust client radios used on carts
To support the pick-to-light functions and WLAN communications, the RF PicKarts have an onboard 16-bit microprocessor that communicates to the WLAN through a UART connection. The microprocessor also supports two serial channels for bar-code scanners and a serial printer. The displays and push buttons interface to the microprocessor through the address/data bus. The carts’ pick-to-light displays and push buttons are mounted on a faceplate for easy visibility. All of the electronics are powered by a built-in 12 V lead-acid battery that can provide power for up to 12 hours between charges.
Deviceservers make design straightforward
For the RF wireless link, IPTI initially chose the Lantronix WiBox, a wireless device server module that creates a transparent data tunnel between an RS-232 serial connection on the RF PicKart microprocessor and the 802.11b/g WLAN. The WiBox was interfaced to the RF PicKart in a couple of days, and a working wireless demonstration was completed in less than one week.
To provide tighter integration of the WLAN interface in the PicKart at a lower price point, IPTI upgraded the RF PicKart design to use the Lantronix MatchPort b/g (Figure 2), anembeddedradio module that easily integrates an 802.11b/g link directly onto the main CPU board. The module interfaces to the host processor’s UART and transparently tunnels data from the host to the server without requiring any special software driver development.
Figure 2:The MatchPort b/g provides an easy way to integrate an 802.11b/g link onto the main CPU board.
On power-up, the MatchPort b/g is configured to make aTCPconnection directly to the back-end server, which runs four turnkey software programs for a complete solution. The software modules include the Host Interface program, Real-Time Pick-to-Light program, IPTI Statistics program, and the Order Reconciliation program. The Host Interface program is themiddlewarethat processes order information to be used in the pick-to-light system. The Real-Time Pick-to-Light program shows the orders that are active in the system and sends order picking details across the WLAN network to the displays. Communication is event-driven, so when the push buttons are pressed, the system acknowledges those events inreal time.
For WLANsecurity, IPTI uses IEEE 802.11Wi-FiProtected Access (WPA) Temporal Key Integrity Protocol Pre-Shared Key security. To set up the security, a few simple configuration settings are established through the serial or network interface. A Web-based configuration manager is also available. For data security from the pick-to-light displays all the way through to the server, the system offers support for optional 256-bit AdvancedEncryptionStandard, enabling secure end-to-end data transfer. For applications that require enterprise-grade WLAN security, the MatchPort b/g Pro offers enhanced features, including WPA2 Transport Layer Security (TLS), Tunneled TLS, or Protected Extensible Authentication Protocol.
The MatchPort b/g is pretested for European telecommunications regulations and FCC certified, which allowed IPTI to leverage the FCC license grant and bypass 802.11 regulatory testing, speeding time to market and minimizing development and testing costs.
Fitting in the network
One problem identified during application testing was roaming. Larger deployments with more than one Access Point (AP) experienced some delays or dropped TCP connections between the RF PicKart and the enterprise server when the carts traveled between APs in the warehouse. Evidently, roaming is not handled the same by all AP vendors. The MatchPort b/g thus could not maintain a seamless association between the different APs as the carts moved around the warehouse.
To solve this problem, Lantronix implemented SmartRoam technology, which enables the MatchPort b/g to continuously track the signal strength of all APs within range that meet the network and security profile. If a stronger AP is available, the module will make a seamless transition to the better AP. This greatly enhanced the mobility of the RF PicKart within a large warehouse and resolved all of the roaming issues.
For the WLAN infrastructure, IPTI chose the Cisco AP1231 APs, which set the enterprise standard for high-performance, secure, manageable, and reliable WLAN networks. These APs provide robust communications in noisy environments, a particularly important feature in warehouse environments where multiple vehicles and excessive RF traffic make it difficult to obtain good link margins. The Cisco APs also offer extensive debugging facilities and the ability to log debug messages with time stamps. These debug features were helpful when troubleshooting the roaming issues.
WLANs solve embedded challenges
Continuous process improvement is demanding cost-effective ways to solve tough supply chain management issues. Secure and robust WLAN networks are providing solutions to these challenges. The order picking process is just one area where WLAN-enabled carts are allowing companies to remain competitive by doing more with less. On a wider scale, many more creative applications can utilize embedded WLAN technology to solve problems with similar ease.
While mobile device display
performance continues to increase, system chip processes geometries
continue to shrink, resulting in a greater proportion of system power
consumed by the display and its high-speed interface. The new EmbeddedDisplay
Port (eDP) v1.4 standard offers several new features that maximize
system power efficiency, further consolidate the display interface, and
address a wide range of system profiles to satisfy the growing demand
for power optimization in the embedded display system.
The importance of lowering display-related system power
Today, mobile devices are a major driving force in the electronics industry. Every year new mobile devices are introduced with increased processing capability, better displays, a smaller and lighter form factor, andextended batterylife. Taking into account typical CPU idle time, an average display consumes about 75 percent of system power. While system chip power reduction is accomplished through shrinking semiconductor process geometries, display power reduction comes through improvements in backlight and LCD technologies, as well as new pixel structures.
However, the recent trend toward brighter, higher-resolution displays is driving up display power. The second-generation iPad had a 1024x768 display and a 25 watt-hour battery, while the latest iPod has a 2048x1536 display (a 400 percent pixel increase) and a 42.5 watt-hour battery (a 70 percent power increase), both delivering a 10-hour battery life. The higher-resolution display requires additional pixel-driving circuitry and a higher data rate display interface, as well as fasterGraphics ProcessingUnit (GPU) rendering and display image processing circuitry.
This display power challenge has led to many new architectural developments at the platform level. Reducing display power means longer battery life and less battery capacity requirement and therefore smaller, lighter, and less expensive systems. Rather than being treated as a simple renderingdevice, display deployment has become more integrated into the overallsystem design. The new eDP v1.4 brings many of these concepts together, as explained in the following discussion.
Panel Self Refresh (PSR)
Introduced in eDP v1.3, the PSR function provides a means to lower display-related system power by allowing portions of the GPU and display interface to enter a low-power state during a static display image condition (see Figure 1). When the system enters PSR mode, the remote frame buffer built into the LCD timing controller (Tcon) performs the routine display refresh task, offloading the GPU and display interface. The local frame buffer can then be updated later by the GPU with a new static image (such as when a flashing cursor is turned on or off), or the system can exit from PSR mode to display constantly changing images (such as when playing a video). Because most displays are refreshed 60 times per second, PSR allows the GPU circuits and display interface to remain in a low-power state for most of the system operating time, resulting in significant power savings.
Figure 1:The PSR function helps reduce power by allowing portions of the GPU and display interface to remain in a low-power state during static display image conditions.
PSR with selective frame update
The latest version of eDP enhances the PSR mechanisms by enabling updates to selected regions of the video frame in the Tcon frame buffer. With eDP v1.3, the entire frame must be updated every time any portion of the image changes. With eDP v1.4, only the new portion of the frame requires updating (see Figure 2). This lets the GPU display interface remain active for a shorter duration, further reducing system power.
Figure 2:The latest version of eDP enables a PSR selective update process that further decreases system power.
